soft-core中文翻译_soft-core读音_soft-core用法 - 英语词典 soft-core中文翻译_soft-core读音_soft-core用法 - 英语词典
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soft-core

英 [ˈsɒft kɔː(r)]

美 [ˈsɔːft kɔːr]

adj.  软性色情的; (性描写等)隐晦的,含蓄的

牛津词典

    adj.

    • 软性色情的;(性描写等)隐晦的,含蓄的
      showing or describing sexual activity without being too detailed or shocking

      柯林斯词典

      • (性描写)非赤裸裸的,较隐晦的
        Soft-corepornography shows or describes sex, but not very violent or unpleasant sex, or not in a very detailed way.

        双语例句

        • Then, through the embedded soft-core processor technology based on FPGA, entire system the control, and processing and transmission of data of were achieved by using the co-design approach of hardware and software.
          然后,通过基于FPGA的嵌入式软核处理器技术,采用软硬件协同设计的方法,实现对整个系统功能的控制及数据的处理与发送。
        • The paper built a soft core processor which named NIOS II in the FPGA by using SOPC technology, and running μ C/ OS-ⅱ operating system on the NIOS II soft-core in order to achieve the scheduling of the system task.
          通过使用SOPC技术,在FPGA内部构建了NIOSⅡ软核处理器,并在NIOSⅡ软核上运行μC/OS-Ⅱ操作系统,从而实现了对系统任务的调度。
        • A 40Gb/ s switch IP soft-core with self-dependence intellectual property was realized.
          形成了具有自主知识产权的40Gb/s交换IP软核。
        • Designed the inter-frame decoding IP soft-core, including the motion vector generation module, prediction processing modules and interpolation modules.
          详细设计了帧间解码IP软核,包括运动矢量生成模块、预测处理模块和插值模块。
        • The hierarchical, modular design idea was used in the system which embeds the Nios II soft-core processor system in FPGA. And the on-chip hardware and software designs are completed.
          整个系统采用层次化、模块化的设计思想,将NIOSii软核处理器系统嵌入到FPGA中,完成片上硬件和软件的设计。
        • This paper proposes a new method for embedded system designing, based on FPGA and soft-core CPU.
          提出了一种基于FPGA(现场可编程门阵列)和软核CPU的嵌入式系统设计的新方法。
        • First some algorithms of gray-scale quantifying are analysised and simulated, and then the detailed designs of complex mold sub-module, quantifying sub-module and SDRAM soft-core controller is presented. 4.
          先对灰度量化算法进行了分析和仿真比较,然后详细介绍了复数求模子模块、量化子模块、SDRAM控制器的设计。
        • Design of an Ethernet Interface Based on the Nios Soft-core Processor
          基于Nios软核处理器的以太网接口设计
        • With the establishing of verification and test platform for SDH chip, We realize the function simulation, timing simulation and performance test of the IP soft-core.
          通过建立SDH芯片验证平台和SDH芯片测试平台,实现IP软核的功能仿真、时序仿真和芯片性能测试。
        • It inherits the hardcore, soft-core, DSP, memory, peripheral I/ O and programmable logic.
          它继承了硬核、软核、DSP、存储器外围I∕O及可编程逻辑。